端子番号 |
端子名称 |
I/O |
端子機能 |
1 |
D11 |
I/O |
Databus11 |
2 |
D12 |
I/O |
Databus12 |
3 |
D13 |
I/O |
Databus13 |
4 |
VCC |
- |
+5V |
5 |
D14 |
I/O |
Databus14 |
6 |
VSS |
- |
0V |
7 |
D15 |
I/O |
Databus15 |
8 |
D16 |
I/O |
Databus16 |
9 |
D17 |
I/O |
Databus17 |
10 |
D18 |
I/O |
Databus18 |
11 |
D19 |
I/O |
Databus19 |
12 |
VCC |
- |
+5V |
13 |
D20 |
I/O |
Databus20 |
14 |
VSS |
- |
0V |
15 |
D21 |
I/O |
Databus21 |
16 |
D22 |
I/O |
Databus22 |
17 |
D23 |
I/O |
Databus23 |
18 |
VCC |
- |
+5V |
19 |
D24 |
I/O |
Databus24 |
20 |
VSS |
- |
0V |
21 |
D25 |
I/O |
Databus25 |
22 |
D26 |
I/O |
Databus26 |
23 |
D27 |
I/O |
Databus27 |
24 |
VCC |
- |
+5V |
25 |
D28 |
I/O |
Databus28 |
26 |
VSS |
- |
0V |
27 |
D29 |
I/O |
Databus29 |
28 |
D30 |
I/O |
Databus30 |
29 |
D31 |
I/O |
Databus31 |
30 |
A0 |
I/O |
Addressbus0 |
31 |
A1 |
I/O |
Addressbus1 |
32 |
A2 |
I/O |
Addressbus2 |
33 |
VSS |
- |
|
34 |
A3 |
I/O |
Addressbus3 |
35 |
A4 |
I/O |
Addressbus4 |
36 |
A5 |
I/O |
Addressbus5 |
37 |
A6 |
I/O |
Addressbus6 |
38 |
A7 |
I/O |
Addressbus7 |
39 |
A8 |
I/O |
Addressbus8 |
40 |
VCC |
- |
+5V |
41 |
A9 |
I/O |
Adressbus9 |
42 |
VSS |
- |
0V |
43 |
A10 |
I/O |
Addressbus10 |
44 |
A11 |
I/O |
Addressbus11 |
45 |
A12 |
I/O |
Addressbus12 |
46 |
A13 |
I/O |
Addressbus13 |
47 |
A14 |
I/O |
Addressbus14 |
48 |
VCC |
- |
+5V |
49 |
A15 |
I/O |
Addressbus15 |
50 |
VSS |
- |
0V |
51 |
A16 |
I/O |
Addressbus16 |
52 |
A17 |
I/O |
Addressbus17 |
53 |
A18 |
I/O |
Addressbus18 |
54 |
VCC |
- |
+5V |
55 |
A19 |
I/O |
Addressbus19 |
56 |
VSS |
- |
0V |
57 |
A20 |
I/O |
Addressbus20 |
58 |
A21 |
I/O |
Addressbus21 |
59 |
A22 |
I/O |
Addressbus22 |
60 |
VCC |
- |
+5V |
61 |
A23 |
I/O |
Addressbus23 |
62 |
VSS |
- |
0V |
63 |
A24 |
I/O |
Addressbus24 |
64 |
A25 |
I/O |
Addressbus25 |
65 |
A26 |
I/O |
Addressbus26 |
66 |
DACK0 |
O |
DMA0 acknowledge |
67 |
VCC |
- |
+5V |
68 |
DACK1 |
O |
DMA1 acknowledge |
69 |
VSS |
- |
0V |
70 |
DREQ0 |
I |
DMA0 request |
71 |
DREQ1 |
I |
DMA1 request |
72 |
CS0# |
O |
Chip select 0 |
73 |
CS1# |
O |
Chip select 1 |
74 |
CS2# |
O |
Chip select 2 |
75 |
CS3# |
O |
Chip select 3 |
76 |
BS# |
I/O |
Bus cycle start |
77 |
RD/WR# |
I/O |
Read/Write# |
78 |
VSS |
- |
0V |
79 |
RAS#/CE# |
O |
RAS# for DRAM/SDRAM,CE# for Pseudo-SRAM |
80 |
CAS#/OE# |
O |
CAS# for DRAM/SDRAM,OE# for Pseudo-SRAM |
81 |
CASHH#/DQMUU/WE3# |
O |
Most significant byte selection signal for memory |
82 |
CASHL#/DQMUL/WE2# |
O |
Second byte selection signal for memory |
83 |
CASLH#/DQMLU/WE1# |
O |
Third byte selection signal for memory |
84 |
VCC |
- |
+5V |
85 |
CASLL#/DQMLL/WE0# |
O |
Least significant byte selection signal for memory |
86 |
VSS |
- |
0V |
87 |
RD# |
O |
Read pulse |
88 |
CKE |
O |
SDRAM clock enable control |
89 |
WAIT# |
I |
Hardware wait request |
90 |
NC(BEN?) |
|
|
91 |
VSS |
- |
0V |
92 |
BACK#/BRLS# |
I |
Bus acknowledge in slave mode,bus request in master mode |
93 |
BREQ#/BGR# |
O |
Bus request in slave mode,bus grant in master mode |
94 |
WDTOVF# |
O |
Watchdog timer overflow signal output |
95 |
FTOB |
O |
Free runnnig timer output B |
96 |
VCC |
- |
+5V |
97 |
FTOA |
O |
Free running timer output A |
98 |
VSS |
- |
0V |
99 |
FTI |
I |
Free runninng time input |
100 |
FTCI |
I |
Free running timer clock input |
101 |
RXD |
I |
Serial port data in |
102 |
TXD |
O |
Serial port data out |
103 |
SCK |
I/O |
serial port clock in/out |
104 |
VCC(PLL) |
- |
Power for on chip PLL +5V |
105 |
MD0 |
I |
Mode select0 |
106 |
VSS(PLL) |
- |
0V for on chip PLL |
107 |
MD1 |
I |
Mode select1 |
108 |
CAP1 |
O |
External capacitance ppin for PLL |
109 |
CAP2 |
O |
External capacitance ppin for PLL |
110 |
MD2 |
I |
Mode select2 |
111 |
CKPACK# |
O |
Clock pause acknowledge output |
112 |
CKPREQ#/CKM |
I |
Clock pause request input |
113 |
VCC |
- |
+5V |
114 |
EXTAL |
I |
Pin for connectiong crystal resonator |
115 |
VSS |
- |
0V |
116 |
XTAL |
O |
Pin for connectiong crystal resonator |
117 |
MD3 |
I |
Mode select3 |
118 |
CKIO |
I/O |
System clock input/output |
119 |
MD4 |
I |
Mode select4 |
120 |
MD5 |
I |
Mode select5 |
121 |
VSS |
- |
0V |
122 |
RES# |
I |
Reset in |
123 |
VCC |
- |
+5V |
124 |
IVECF# |
O |
Interrupt vector fetch cycle |
125 |
NMI |
I |
Non maskable interrupt request |
126 |
IRL3# |
I |
External interrupt source request3 |
127 |
IRL2# |
I |
External interrupt source request2 |
128 |
IRL1# |
I |
External interrupt source request1 |
129 |
IRL0# |
I |
External interrupt source request0 |
130 |
D0 |
I/O |
Databus0 |
131 |
D1 |
I/O |
Databus1 |
132 |
VCC |
- |
+5V |
133 |
D2 |
I/O |
Databus2 |
134 |
VSS |
- |
0V |
135 |
D3 |
I/O |
Databus3 |
136 |
D4 |
I/O |
Databus4 |
137 |
D5 |
I/O |
Databus5 |
138 |
D6 |
I/O |
Databus6 |
139 |
VCC |
- |
+5V |
140 |
D7 |
I/O |
Databus7 |
141 |
VSS |
- |
0V |
142 |
D8 |
I/O |
Databus8 |
143 |
D9 |
I/O |
Databus9 |
144 |
D10 |
I/O |
Databus10 |