---------------------------------------------------------------------------- 315-5313 information (C) 2008 Charles MacDonald ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- Specifications ---------------------------------------------------------------------------- - 128-pin plastic QFP - Sega part number: 315-5313 - Yamaha part number: YM-7011 Used in several consoles and arcade platforms: - Sega Genesis - Sega Mega Drive - Sega Mega Tech - Sega Mega Play - Sega System 18 - Sega System C - Sega System C-2 ---------------------------------------------------------------------------- Pin assignments ---------------------------------------------------------------------------- 001: VRAM SD0 002: VRAM SD1 003: VRAM SD2 004: VRAM SD3 005: VRAM SD4 006: VRAM SD5 007: VRAM SD6 008: VRAM SD7 009: (N.C.) 010: VRAM /SE_0 011: VRAM SC 012: VRAM /RAS_1 013: VRAM /CAS_1 014: (N.C.) 015: VRAM /WE_0 016: VRAM /OE_1 017: GND 018: (N.C.) 019: (N.C.) 020: (N.C.) 021: (N.C.) 022: (N.C.) 023: (N.C.) 024: (N.C.) 025: (N.C.) 026: AGC 027: R-VIDEO 028: G-VIDEO 029: B-VIDEO 030: AVC 031: VRAM AD0 032: VRAM AD1 033: VRAM AD2 034: VRAM AD3 035: VRAM AD4 036: VRAM AD5 037: VRAM AD6 038: VRAM AD7 039: /YS 040: SPA/B 041: /VSYNC 042: /C-SYNC 043: /HSYNC 044: /HL 045: SEL0 046: /PAL 047: /RESET 048: SEL1 049: /CLK1 050: SBCR 051: CLK0 052: MCLK 053: EDCLK 054: +5V 055: 68000 D0 056: 68000 D1 057: 68000 D2 058: 68000 D3 059: 68000 D4 060: 68000 D5 061: 68000 D6 062: 68000 D7 063: 68000 D8 064: 68000 D9 065: 68000 D10 066: 68000 D11 067: 68000 D12 068: 68000 D13 069: 68000 D14 070: 68000 D15 071: 68000 A1 072: 68000 A2 073: 68000 A3 074: 68000 A4 075: 68000 A5 076: 68000 A6 077: 68000 A7 078: 68000 A8 079: 68000 A9 080: 68000 A10 081: 68000 A11 082: 68000 A12 083: 68000 A13 084: 68000 A14 085: 68000 A15 086: 68000 A16 087: 68000 A17 088: 68000 A18 089: 68000 A19 090: 68000 A20 091: 68000 A21 092: 68000 A22 093: 68000 A23 094: AVS 095: PSG 096: AGS 097: GND 098: Z80 /INT 099: 68000 /BR 100: 68000 /BGACK 101: 68000 /BG 102: /MRE0 103: /INTAK 104: 68000 /IPL1 105: 68000 /IPL2 106: Z80 /IREQ 107: Z80 /ZRD 108: Z80 /ZWR 109: Z80 /M1 110: 68000 /AS 111: 68000 /UDS 112: 68000 /LDS 113: 68000 R//W 114: 68000 /DTAK 115: /UWR 116: /LWR 117: /OE0 118: /CAS0 119: /RAS0 120: VD0 121: VD1 122: VD2 123: VD3 124: VD4 125: VD5 126: VD6 127: VD7 128: +5V ---------------------------------------------------------------------------- Pin functions ---------------------------------------------------------------------------- Timing signals MCLK : Master clock input CLK0 : Outputs MCLK / 15 /CLK1 : Outputs MCLK / 7 SBCR : Outputs MCLK / 15 (when /PAL=H) Outputs MCLK / 12 (when /PAL=L) EDCLK : Unknown In a typical system MCLK is 53.694175 which yields: CLK0 = 3.58 MHz (Z80 clock) /CLK1 = 7.67 MHz (68K and YM2612 clock) SBCR = 3.58 MHz (/PAL=H, NTSC color subcarrier) = 4.48 MHz (/PAL=L, PAL color subcarrier) EDCLK = Unknown Configuration inputs SEL0 : 0= VDP operates in Mark-III compatibility mode 1= VDP operates in normal mode SEL1 : Unknown Tied to GND in Sega Genesis, Mega Play. Tied to +5V in System C2 and System 18. /PAL : 0= VDP generates PAL compatible display timings 1= VDP generates NTSC compatible display timings Miscellaneous /HL : Horizontal counter latch enable. On a negative transition the horizontal counter is latched and can be read back by the CPU. It remains latched as long as /HL is held low, otherwise it is free-running. /RESET : Reset input. 68000 interface D15-D0 : Data bus A23-A1 : Address bus /BR : Bus request /BGACK : Bus grant acknowledge /BG : Bus grant /IPL2 : Interrupt priority level, bit 2 /IPL1 : Interrupt priority level, bit 1 /AS : Address strobe /UDS : Upper data strobe /LDS : Lower data strobe /R/W : Read/write indicator /DTACK : Data acknowledge Host interface /INTAK : Asserted to acknowledge a VDP-generated interrupt on IPL2-1. An external circuit would assert this when FC2-0 are high and /AS is low. /LWR : Asserted when /LDS=L, /R/W=L. Used as the lower byte lane strobe. /UWR : Asserted when /UDS=L, /R/W=L. Used as the upper byte lane strobe. /CAS0 : Asserted when /AS=L, /R/W=H within address range 000000-DFFFFF. During DMA, it is asserted for 000000-FFFFFF. Hardware depending on it's restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range. Because this signal overlaps the VDP area at $C00000-$DFFFFF, it is insufficient to use directly as a chip select despite being qualified by /AS. If it was (for example) gated with A23, it could be used directly as ROM /OE for fast ROM access when ROM /CS is tied low. Typically used as a read strobe, and the address decoding logic restricts other devices from responding to it when an address is within the VDP range. /RAS0 : Asserted when /AS=L within address range E00000-FFFFFF. During DMA, it is asserted for 800000-FFFFFF. Hardware depending on it's restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range. Typically used as work RAM /CS with RAM mapped to E00000-FFFFFF. Periodically the VDP will stretch a /RAS0 cycle longer than normal, and insert an extra /OE0 pulse. This may be to provide a refresh cycle for pseudo-static RAMs. /OE0 : Asserted when /R/W=H within address range E00000-FFFFFF. During DMA, it is asserted for 000000-FFFFFF. Hardware depending on it's restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range. Typically used as work RAM /OE with RAM mapped to E00000-FFFFFF. Refresh behavior Periodically /RAS0 is delayed, and an extra /OE0 pulse is added. /MRE0 : Unknown. Tied to +5V in System C2. Controlled by the glue logic chip in the Genesis/MegaDrive. Z80 interface /INT : Interrupt request /IREQ : I/O access /ZRD : Read strobe /ZWR : Write strobe /M1 : Opcode fetch strobe It is not clear how the VDP knows when to respond to the Z80 for accesses to $7F00-$7F1F, which map to $C00000-$C0001F. It could be that the glue logic chip forwards this request on the 68000 bus. When in Mark-III compatibility mode, the Z80 address and data bus are routed to the 68000 address and data bus. This way the VDP can check /IREQ to determine when ports $40-$7F and $80-BF are being accessed, and respond to them accordingly. VRAM interface signals SD7-0 : Serial data bus AD7-0 : Parallel address/data bus /SE_0 : Serial data bus /OE SC : Serial clock /RAS_1 : Row address strobe /CAS_1 : Column address strobe /WE_1 : Common write strobe /OE_1 : Common read strobe Video sync signals The function of /VSYNC is defined by bit 6 of VDC register $0C: 0= Pin outputs vertical sync. pulse. 1= Pin outputs pixel clock. The function of /HSYNC is defined by bit 5 of VDC register $8C: 0= Pin outputs horizontal sync. pulse. 1= Pin is fixed to 'H' /C-SYNC outputs a composite sync signal. It is TTL like /VSYNC and /HSYNC. Video output R-VIDEO,G-VIDEO,B-VIDEO are the analog RGB outputs. AGC and AVC should be tied to +5V and GND respectively. Sound output PSG is the analog audio output from the SN76489-alike programmable sound generator in the VDP. AVS and AGS should be tied to +5V and GND respectively. Color bus The color bus outputs information about the pixel data being displayed: /Y1 : 0= Transparent pixel, 1= Opaque pixel SPA/B : 0= Sprite pixel, 1= Non-sprite pixel VD7 : Hilight effect (0= not applied, 1= applied) VD6 : Shadow effect (0= not applied, 1= applied) VD5 : Palette, bit 1 VD4 : Palette, bit 0 VD3 : Pixel, bit 3 VD2 : Pixel, bit 2 VD1 : Pixel, bit 1 VD0 : Pixel, bit 0 /Y1 and SPA/B can be decoded as follows: /Y1 A/B 0 0 : Transparent pixel from any layer. 0 1 : (This condition never occurs) 1 0 : Opaque pixel from sprite layer. 1 1 : Opaque pixel from background or backdrop layers. VD7 and VD6 can be decoded as follows: VD7 VD6 0 0 : Normal 0 1 : Shadow 1 0 : Hilight 1 1 : (This condition never occurs) Unknown pins Pins 9, 14, 18-25 seem to be no-connects and have no known function. ---------------------------------------------------------------------------- Comments ---------------------------------------------------------------------------- 68000 access The VDP handles it's own address decoding rather than having a dedicated /CS input. When the address bus matches this pattern: (address & 0xE700E0) == 0xC00000 the VDP will respond. This maps it to certain offsets within the $C00000-$DFFFFF range. Only bits A4-A1 are used to decode internal addresses, the remaining locations are mirrors. Addresses are: $C00000 : Data port $C00002 : Data port (mirror) $C00004 : Control port $C00006 : Control port (mirror) $C00008 : HV counter $C0000A : HV counter (mirror) $C0000C : HV counter (mirror) $C0000E : HV counter (mirror) $C00010 : PSG data $C00012 : PSG data (mirror) $C00014 : PSG data (mirror) $C00016 : PSG data (mirror) $C00018 : Unused $C0001A : Unused (mirror) $C0001C : Test register $C0001E : Test register (mirror) ---------------------------------------------------------------------------- End ----------------------------------------------------------------------------